Figure 2 from Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
Figure 1 from Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
The Next-Generation Interconnect | Mouser
USB 2.0 OTG IP Core | Arasan Chip Systems
Mixed-Signal Verification for USB 2.0 Physical Layer IP
High Speed Inter-CHIP USB 2.0 PHY | Arasan Chip Systems
USBPHYC internal peripheral - stm32mpu
USB 2.0 Full High Speed Solution | NXP Semiconductors
DWTB: USB High Speed Inter-Chip (HSIC) IP: What is it? And why should I use it?
USB 2.0 Device Controller for SoC Designs | Cadence IP
TUSB1210-Q1 data sheet, product information and support | TI.com
Amazon.com: Plugable Adaptador USB 2.0 a Gigabit Ethernet, conexión Gigabit rápida y fiable, compatible con Windows, Chromebook, Linux : Electrónica
Teledyne LeCroy - USB and USB Type-C® Electrical Test Solutions
USB 2.0 PHY Verification
USB2.0 Soft IP: An Introduction to GOWIN Semiconductor's USB Solution for FPGA's - YouTube
USB 3.0/2.0 Combo PHY IP for SoC Designs | Cadence IP
XPS USB 2.0 Host Controller
TUSB1210 data sheet, product information and support | TI.com
USB2 Controller | Cadence
HSIC USB 2.0 PHY IP
USB 2.0 Full High Speed Solution | NXP Semiconductors
USB2 PHY | Cadence
USB 2.0 PHY IP Core Device Host OTG Hub in TSMC, 28HPC, 40LP /LL, UMC, 40LP, 28HPC, SMIC 14SF, SF, 55LL, 40LL - T2M-IP
USB v2.0 Soft PHY and Device Controller
USB2.0 PHY – Silicon Library Inc.
Soft Mixed Signal Corporation USB 2.0 PHY IP Cores
